It is designed to meet the electrical characteristics required for reliable data transmission in noisy environments. The diagram below shows potentials of the A (blue) and B (red) pins of an RS-485 line during transmission of one byte (0xD3, least significant bit first) of data using an asynchronous start-stop method. A FIFO is a First In/First Out buffer that can queue a burst of outgoing characters for transmission, or save a set of incoming characters until the host can read them. Serial data is shifted out least-significant-bit first. If more than one slave tried to drive the transmit line simultaneously, their serial drivers would fight with each other for control of the bus. In the most common multi-drop RS485 protocol, one computer is designated as a master and the rest of the computers or devices on the serial bus are designated as slaves. The remaining inactive slaves may actively receive, or listen to, data on the communications line, rs485 cable but only one slave at a time can transmit a message. At any given time, only the master and a single active slave communicate.

To ensure that no two devices drive the network at the same time, it is necessary that each slave device be able to disable its own RS485 data transmitter. 2) The RS-232 standard for serial communication interfaces between DTE and DCE devices. So long as the error between the actual baud rate and that specified is less than 1.5% (or the error between transmitter and receiver is less than 3%) there should be no communication errors. The Serial2 channel is always configured for RS232 communications, and can sustain baud rates up to 4800 baud. The PDQ Board controls the Serial1 and Serial2 RS485 transceivers with bits PJ0 and PJ1, respectively, of PORTJ of the processor. When the keyword name is received by the Silence() routine running in the slave, the slave PDQ Board executes RS485Transmit() to send an acknowledgment to the master (which should now be listening to the serial bus to accept the acknowledgment). RS485Receive() to wait for any pending character transmission to complete, then disable the transmitter, and then execute a routine such as Key() to listen to the communications on the serial bus.

This allows RS-485 to implement linear bus topologies using only two wires. One to two logic-high stop bits mark the end of a character. In other words, each local UART on the wildcard can both send data to and receive data from a remote UART on the other end of a connecting serial cable. At the end of a received character, the service routine takes about 45 µs. The Silence() routine searches the incoming serial characters for a pre-determined keyword (for example, the ascii name of this particular slave). The above parity settings will also determine how incoming data is interpreted (whether the most significant bit is considered a parity bit or part of the data being transmitted, and how many bits total to expect in each byte). Each of the two channels on the UART Wildcard implements two 16-character FIFOs, one for outgoing characters and one for incoming characters. Each of the two channels on the UART Wildcard can be configured for RS232, RS422, or RS485. You can use one or both of the PDQ Board’s RS485 links to create such a multi-drop serial network.

With one sing coaxial cable, both the video data transmission and PTZ Control are achievable. The words port and channel are used interchangeably to refer to a serial communications link. Since both channels can operate simultaneously and independently, debugging can be performed while the application program is communicating via its primary channel. The UART Wildcard implements these optional RS232 modem handshaking signals on channel 1. The handshaking signals can be disabled and/or ignored by applications that do not need them. Hardware is interfaced to the SPI via three PORTD pins named SCK, MOSI, and MISO brought out to pins 7, 8, and 10 on the Wildcard Port Header (see Appendix B). The UART Wildcard supports any baud rate produced by the above formula. Software-selectable baud rates up to 56,000 baud are supported. Baud rates up to 56,000 baud are supported. Both the local and remote UARTs must be configured for the same baud rate. Rather, the transmitter and receiver must be communicating using a known baud rate, or bit frequency. Bauddesired is an unsigned integer from 1 to 56000, 500000 is the frequency of the UART's internal clock and Round(500000/Bauddesired) is an internal divisor (rounded to the nearest integer).